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VIS
Description
4 (word x bit x bank), respectively.
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
* Single 3.3V ( 0.3V ) power supply * High speed clock cycle time -6 : 166MHz<3-3-3>, available only on 4MX16 option -7 : 143MHz<3-3-3>, 133MHz<2-3-2> -7L: 133MHz<3-3-3> -8H: 100MHz<2-2-2> * Fully synchronous operation referenced to clock rising edge * Possible to assert random column access in every cycle * Quad internal banks controlled by A12 & A13 (Bank Select) * Byte control by LDQM and UDQM for VG36641641D * Programmable Wrap sequence (Sequential / Interleave) * Programmable burst length (1, 2, 4, 8 and full page) * Programmable /CAS latency (2 and 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * X4, X8, X16 organization * LVTTL compatible inputs and outputs * 4,096 refresh cycles / 64ms * Burst termination by Burst stop and Precharge command
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Pin Configurations
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
VG36644041 ( x4 ) VG36648041 ( x8 ) VG36641641 ( x16 ) VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC /WE /CAS /RAS /CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE /CAS /RAS /CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE /CAS /RAS /CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE NC
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
Pin Descriptions Pin Name CLK CKE /CS /RAS
/CAS /WE DQ0 ~ DQ15
Function Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O
Pin Name DQM A0-11 BA0,1 VDD VDDQ VSS VSSQ
Function DQ Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
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Block Diagram
CLK CKE Clock Generator
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
Bank D Bank C Bank B
Bank A
Command Decoder
Sense Amplifier Control Logic Column Address Buffer & Burst Counter Column Decoder & Latch Circuit Input & Output Buffer Latch Circuit
CS RAS CAS WE
DQM
Data Control Circuit
DQ
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Pin Function
Symbol CLK CKE Input Input Input
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Function Maste Clock: Other inputs signals are referenecd to the CLK rising edge Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The row address is specified by A0-A11. The column address is specified by A0-A9 (X4) / A0-A8 (X8) / A0-A7 (X16) Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands (row address A0A10), and the column address and AUTO PRECHARGE bit for READ/WRITE commands (column address A0-A7 with A10 defining AUTO PRECHARGE), to select one location out of the memory array in the respective bank. Data Input / Output: Data bus
/CS
Input
/RAS, /CAS, /WE A0 - A13
Input Input
BA0,BA1 DQM, UDQM , LDQM
Input Input
DQ0 - DQ15 VDD, VSS VDDQ, VSSQ
I/O
Supply Power Supply for the memory array and peripheral circuitry Supply Power Supply are supplied to the output buffers only
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Absolute Maximum Ratings
Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VDD VDDQ VI VO IO PD TOPT TSTG
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Conditions with respect to V SS with respect to V SSQ with respect to V SS with respect to V SSQ Ta = 25 C
Value -0.5 to 4.6 -0.5 to 4.6 -0.5 to V DD+0.5 -0.5 to VDDQ+0.5 50 1 0 to 70 -65 to 150
Unit V V V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (Ta = 0 ~ 70 C, unless otherwise noted)
Parameter Supply Voltage Supply Voltage for DQ Ground Ground for DQ High Level Input Voltage (all inputs) Low Level Input Voltage (all inputs) Symbol VDD VDDQ VSS VSSQ VIH VIL Limits Min. 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 VDD + 0.3 0.8 Unit V V V V V V
Pin Capacitance (Ta = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Input Capacitance, address & control pin Input Capacitance, CLK pin Data input / output capacitance Symbol CIN CCLK CI/O Min 2.5 2.5 4.0 Max 3.8 3.5 6.5 Unit pF pF pF
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Parameter Operating current Symbol ICC1 Test Conditions
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
DC Characteristics 1 (Ta = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0V, Ouput Open, unless otherwise noted)
Organization x4 x8 x16 x4/x8/x16 x4/x8/x16 x4/x8/x16 -6 95 Limits (max.) -7 -7L 75 75 75 75 85 85 2 1 20 mA -8H 70 70 80 Unit Notes
One bank active tRC = tRC(MIN), tCLK = tCLK(MIN), BL = 1, CL=3
mA
1, 2
Precharge standby ICC2P CKE VIL(MAX), tCK = 15ns current in power down ICC2PS CKE VIL(MAX), CLK VIL(MAX) mode Precharge standby ICC2N CKE V CC - 0.2V CS current in non power CKE tCK = 15ns, CKE V IH(MIN) down mode ICC2NS CKE V CC - 0.2V CS CLK VIL(MAX), CKE VIH(MIN) CKE V All input signals are stable. CKE
mA
3
x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8/x16
15 7 5 30
mA
Active standby current ICC3P in power down mode ICC3PS Active standby current ICC3N in Nonpower down mode ICC3NS
VIL(MAX), tCK = 10ns CKE VIL(MAX), CLK VIL(MAX) CS CKE V CC - 0.2V CKE tCK = 15ns, CKE V IH(MIN) CKE V CC - 0.2V CS CLK VIL(MAX), CKE VIH(MIN) CKE V
All input signals are stable. All banks active tCK = tCK(MIN), BL=4, CL=3 All banks active tRC = tRC(MIN) , tCLK = tCLK(MIN) CKE
mA
mA
3
x4/x8/x16 x4 x8 x16 x4/x8/x16 x4/x8/x16 130 150 90 90 100 130
25 90 90 100 130 1 0.5 70 70 80 110
mA
Operating current (Burst mode) Refresh current Self refresh current NOTES
ICC4
mA mA mA mA 4 5
ICC5 ICC6
0.2V
1. ICC(max) is specified at the output open condition. 2. -6 grade is available only on 4MX16 option. 3. Input signals are changed one time during 30ns. 4. Normal version: VG366440(80/16)41DT 5. Low power version: VG366440(80/16)41DTL
DC Characteristics 2 (Ta = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Input leakage current (Inputs) Output leakage current (I/O pins) High level output voltage Low level output voltage Symbol II (L) IO (L) VOH VOL Test Condition 0 VIN VDD(MAX) Pins not under test = 0V 0 VOUT VDD(MAX) DQ# in H - Z., DOUT is disabled IOH = -2mA IOL = 2mA Min -5 -5 2.4 0.4 Max 5 5 Unit uA uA V V
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Test Conditions AC input Levels (VIH/VIL)
Input rise and fall time 2.0 / 0.8V 1ns
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
AC Characteristics (Ta = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Input timing reference level / Output timing reference level Output load condition
1.4V 50pF
Note): 1.if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Output Load Conditions
VDDQ VOUT
VDDQ
Z = 50
50PF
Device Under Test
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Parameter Symbol Min CLK cycle time CL = 3 CL = 2 CLK to valid output delay CLK high pulse width CLK low pulse width CKE setup time CKE hold time Address setup time Address hold time Command setup time Command hold time Data input setup time Data input hold time Output data hold time CL = 3 CL = 2 CL = 3 CL = 2 tCK3 tCK2 tAC3 tAC2 tCH tCL tCKS tCKH tAS tAH tCMS tCMH tDS tDH tOH3 tOH2 tLZ tHZ tRC tRAS tRCD tRP tRRD tDPL tT tRSC tREF 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 2.5 2.5 0 2.5 60 42 18 15 12 12 1 2 64 10 100K 5 6 7.5 5 6 -6
*1
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Limits -7 Max Min 7 7.5 5.4 6 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 2.7 2.7 0 2.7 63 42 20 15 14 14 1 2 64 10 100K 5.4 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 2.7 3 0 2.7 67.5 45 20 20 15 15 1 2 64 10 100K 5.4 Max Min 7.5 10 5.4 6 3 3 2 1 2 1 2 1 2 1 3 3 0 3 70 50 20 20 20 20 1 2 64 10 100K 6 -7L Max Min 8 10 6 6 -8H Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tck ms *2 *2 *2 *2 Unit Note
CLK to output in low - Z CLK to output in H - Z ROW cycle time ROW active time RAS to CAS delay Row precharge time Row active to active delay Data in to precharge Transition time Mode reg. set cycle Refresh time
Notes 1. -6 grade is available only on 4MX16 option. 2. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
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Basic Features and Function Description
1. Simplified State Diagram
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Self
Refresh
try en it ex
LF SE
Mode Register Set
MRS
IDLE
LF SE
REF
AUTO Refresh
CK E
E CK
ROW ACTIVE
BS T
ACT
Power Down
CKE CKE
T BS
Active Power Down
ad Re
W rit e
Au Write to p red with har ge
h wit rge ad cha Re Pre to Au
re co ve r
y
Write (Write recovery)
Read
PRE
W
rit
e
WRITE SUSPEND
CKE CKE
WRITE
Read (write recovery) Write
READ
CKE CKE
READ SUSPEND
Write with Auto Precharge
R Auto ead w Pre ith cha rge
rge cha P re E( PR
ith e te w arg Wri Prech uto (writA
e re cov ery)
ter min atio n )
Read with Auto Precharge
WRITE A SUSPEND
CKE CKE
WRITE A
CKE READ A CKE
READA SUSPEND
POWER ON
Precharge
Precharge
Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state
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2.Truth Table 2.1 Command Truth Table
FUNCTION Device deselect No operation Mode register set Bank activate Read Read with auto precharge Write Write with auto precharge Precharge select bank Precharge all banks Burst stop CBR (Auto) refresh Self refresh Symbol DESL NOP MRS ACT READ READA WRIT WRITA PRE PALL BST REF SELF CKE n-1 H H H H H H H H H H H H H n
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
CS H L L L L L L L L L L L L
RAS X H L L H H H H L L H L L
CAS X H L H L L L L H H H L L
WE X H L H H H L L L L L H H
BA X X L V V V V V V X X X X
A10 X X L V L H L H L H X X X
A11 A9 - A0 X X V V V V V V X X X X X
X X X X X X X X X X X H L
2.2 DQM Truth Table
CKE FUNCTION Data write/output enable Data mask/output disable Symbol ENB MASK n-1 H H n-1 X X L H DQM
2.3 CKE Truth Table
CKE Current State Activating Any Clock suspend Idle Idle Self refresh Idle Power down Function Clock suspend mode entry Clock suspend Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit REF SELF Symbol n-1 H L L H H L L H L n L L H H L H H L H CS X X X L L L H X X RAS X X X L L H X X X CAS X X X L L H X X X WE X X X H H H X X X Add ress X X X X X X X X X
H : High level, L : Low level X : High or Low level (Don't care), V : Valid Data input
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2.4 Operative Command Table (note 1)
HCurrent state CS Idle H L L L L L L L Row active H L L L L L L L Read H L L L L L L L L Write H L L L L L L L L RAS CAS WE X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Address
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
(1/3)
Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MPS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Nop or Power down Nop or Power down ILLEGAL ILLEGAL Row active Nop Refresh or Self refresh Mode register access Nop Nop Begin read : Determine AP Begin write : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop 5 5 3 6 4 Notes 2 2 3 3
Row active Row active
7 7,8 3
Row active
Term burst, new read : Determine AP Term burst, start write : Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop
write recovering write recovering
7,8 7 3 9
Row active
Term burst, start read : Determine AP Term burst, new write : Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL
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Current state Read with auto precharge CS RAS CA WE H L L L L L L L L Write with auto precharge H L L L L L L L L Precharging H L L L L L L L L Row activating H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code Address
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
(2/3) Command DESL NOP BST WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST Action Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end write recovering with auto precharte Continue burst to end write recovering with auto precharge ILLEGAL 11 11 3,11 3,11 Notes Precharging Precharging 11 11 3,11 3,11

READ/READA ILLEGAL
READ/READA ILLEGAL WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Nop Nop

Enter idle after tRP Enter idle after tRP Enter idle after tRP 3 3 3
READ/READA ILLEGAL WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST ILLEGAL ILLEGAL Nop
Enter idle after tRP
ILLEGAL ILLEGAL Nop Nop Nop

Enter row active after tRCD Enter row active after tRCD Enter row active after tRCD 3 3 3, 9 3
READ/READA ILLEGAL WRIT/WRITA ACT PRE/PALL REF/SELF MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
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Current Write recovering CS H L L L L L L L L Write recovering with auto precharge H L L L L L L L L Auto Refreshing H L L L L Mode register setting H L L L L RAS X H H H H L L L L X H H H H L L L L X H H L L X H H H L CAS X H H L L H H L L X H H L L H H L L X H L H L X H H L X WE X H L H L H L H L X H L H L H L H L X X X X X X H L X X X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X X X X X X X X Address
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
(3/3) Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL DESL NOP BST READ/WRITE Nop Nop Nop Action Notes

Enter row active after tDPL Enter row active after tDPL Enter row active after tDPL 8 3 3
Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Nop Nop

Enter precharge after tDPL Enter precharge after tDPL Enter precharge after tDPL 3,8,11 3,11 3,11 3
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC Nop Enter idle after tRC ILLEGAL ILLEGAL Nop Nop
REF/SELF/MRS ILLEGAL

Enter idle after 2 Clocks Enter idle after 2 Clocks
ILLEGAL ILLEGAL
ACT/PRE/PALL/ ILLEGAL REF/SELF/MRS
Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA), state of that bank. 4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but legal for other banks in multi-bank devices.
depending on the
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2.5 Command Truth Table for CKE (Note 1)
Current state Self refresh (S.R.) CKE n-1 H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L CKE n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X
Address X X X X X X X X X X X X X X X X X
Action INVALID, CLK (n - 1)would exit S.R. S.R. Recovery S.R. Recovery ILLEGAL ILLEGAL Maintain S.R. Idle after tRC Idle after tRC ILLEGAL ILLEGAL Begin clock suspend next cycle Begin clock suspend next cycle ILLEGAL ILLEGAL Exit clock suspend next cycle Maintain clock suspend INVALID, CLK (n - 1) would exit P.D.
Notes
2 2
Self refresh recovery
5 5
2
Power down (P.D.) Both banks idle
EXIT P.D. Idle X Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operation in Operative Command Table X Auto Refresh Op - Code Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table X Self refresh Op - Code Refer to operations in Operative Command Table X X X X X Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
2
3
3
Any state other than listed above
4
Note: 1. H : Hight level, L : low level, X : High or low level (Don't care). 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. Illegal if tSREX is not satisfied.
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3.Initiallization
malfunctioning.
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or
1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs. 2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all bank. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode regiser. After these sequence, the SDRAM is in idle state and ready for normal operation.
4.Programming the Mode Register
The mode register is programmed by the mode register set command using address bits A13 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options CAS latency Wrap type Burst length : A13 through A7 : A6 through A4 : A3 : A2 through A0
Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed.
CAS Latency
CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed, the output bus will become high impedance. The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system.
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5.Mode Register 13 12 11 000 13 12 11 x xx 13 12 00 11 0 6 6 6 10 0 10 x 10 0 9 0 9 1 9 0 8 0 8 0 8 0 7 1 7 0 7 0 5 4 LTMODE 4 LTMODE 5 3 WT 3 WT 5 4 3
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
2 2 2
1 1 BL 1 BL
0
JEDEC Standard Test Set
0
Burst Read and Single Write (for Write Through Cache)
0
Burst Read and Burst Write X = Don't care
Bits2 - 0 WT = 0 WT = 1 1 000 1 001 010 Burst length 011 100 101 110 111 Wrap type 0 1
2 4 8 R R R
Fullpage
2 4 8 R R R R
Sequential Interleave
Bits 6-4 000 001 010 Latency mode 011 100 101 110 111
CAS Iatency R
R 2 3 R R R
R
Remark R : Reserved
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5.1 Burst Length and Sequence
(Burst of Two) Starting Address (column address A0, binary) 0 1 (Burst of Four) Starting Address (column address A1 - A0, binary) 00 01 10 11 (Burst of Eight) Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 0, 1 1, 0
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Sequential Addressing Sequence (decimal)
Interleave Addressing Sequence (decimal) 0, 1 1, 0
Sequential Addressing Sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2
Interleave Addressing Sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
Sequential Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1 ,2 4, 5, 6, 7, 0, 1, 2, 3 5, 6 ,7, 0, 1, 2, 3, 4 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 7, 0, 1, 2, 3, 4, 5, 6
Interleave Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 1,024 (for 16Mx4), 512 (for 8M x 8) and 256 (for 4Mx16).
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6.Address Bits of Bank-Select and Precharge
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (Activate command)
A12 0 0 1 1
A13 0 1 0 1
Result Select Bank A "Activate " command Select Bank B "Activate" command Select Bank C "Activate" command Select Bank D "Activate" command
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (Precharge command)
A10 0 0 0 0 1
A12 A13 Result 0 0 1 1 X 0 1 0 1 X Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
X: Don't care
0 1 Co1. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (CAS strobes)
Disables Auto-Precharge (End of Burst) Enables Auto - Precharge (End of Burst) A12 0 0 1 1 A13 0 1 0 1 Result Enables Read/Write commands for Bank A Enables Read/Write commands for Bank B Enables Read/Write commands for Bank C Enables Read/Write commands for Bank D
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7.Precharge
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
The precharge command can be asserted anytime after tRAS(min.) is satisfied. Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
PrechargeE
T0 CLK Command Read
T1
T2
T3
T4
T5
T6
Burst lengh=4 T7
PRE CAS latency = 2 DQ Q0 Q1 Q2 Q3 Hi - Z
Command CAS latency = 3 DQ
Read
PRE
Q0
Q1
Q2
Q3
Hi - Z
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter "tDPL " must be satisfied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be calculated by dividing t DPL(min.) with the clock cycle time. In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL(min.) + tDPL(min.)
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8.Auto Precharge
begins automatically.
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged. When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has been satisfied. A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles. The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write.
8.1 Read with Auto Precharge During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word output.
READ with AUTO PRECHARGE
Burst lengh = 4 T0 T1 T2 T3
T4
T5
T6
T7
T8
CLK
No New Command to Bank B
Command
READA B
Auto precharge starts
CAS latency = 2 DQ QB0 QB1 QB2 QB3 Hi - Z
No New Command to Bank B
Auto precharge starts Command CAS latency = 3 DQ Remark READA means READ with AUTO PRECHARGE QB0 QB1 QB2 QB3 Hi - Z
READA B
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8.2 Write with Auto Precharge word input to the device.
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data
WRITE with AUTO PRECHRGE
Burst lengh = 4 T0 CLK Command
WRITA B
AUTO PRECHARGE starts
T1
T2
T3
T4
T5
T6
T7
T8
CAS latency = 2 DQ
DB0 DB1 DB2
tDPL
Hi - Z_
DB3
Command CAS latency = 3 DQ
AUTO PRECHARGE starts
WRITA B
tDPL
Hi - Z
DB0
DB1
DB2
DB3
Remark WRITA means WRITE with AUTO Precharge
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL(min.) + tDPL(min.)
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9. Read / Writw Command Interval
9.1 Read to Read Command Interval
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Read A Read B
Command
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
9.2 Write to Write Command Interval During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will begin with a new write command. WRITE will be interrupted by another WRITE. Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Write A Write B
Command
DQ
QA0
QB0
QB1
QB2
QB3
Hi-Z_
1 cycle
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9.3 Write to Read Command Interval
WRITE to READ Command Interval
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK 1 cycle Command CAS latency=2 Hi-Z WRITE A Read B
DQ
DA0
QB0
QB1
QB2
QB3
Command
Write A
Read B
CAS latency=3 DQ DA0 Hi-Z QB0 QB1 QB2 QB3
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write.
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READ to WRITE Command Interval
T0 T1 T2
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
T3
T4
T5
T6
T7
CAS latency=2 T8
CLK
Command
Read
Write
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
T0
T1
T2
T3
T4
T5
T6
T7
Burst length=8, CAS latency=2 T9 T8
CLK
Command
Read
Write
DQM
DQ
Q0
Q1
Q2 Hi-Z is necessary
D0
D1
D2
example: Burst length=4, CAS latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
Command
Read
Write
DQM
DQ
Q2
Hi-Z is necessary
D0
D1
D2
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10.BURST Termination
10.1 BURST Stop Command
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command.
During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command. During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to Hi-Z at the same clock with the burst stop command.
Burst Termination
T0
T1
T2
T3
T4
T5
Burst lengh=X, CAS Intency=2,3 T7 T6
CLK BST
Command
Read
CAS latency=2 DQ
Q0
Q1
Q2
Hi-Z
CAS latency=3 DQ
Q0
Q1
Q2
Hi-Z
Remark BST: Burst stop command
T0
T1
T2
T3
T4
T5
Burst lengh=X, CAS latency=2,3 T7 T6
CLK BST
Command
Write
CAS latency=2,3 Q0 DQ Q0 Q1 Q2 Hi-Z_
Remark BST: Burst command
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10.2 PRECHARGE TERMINATION 10.2.1 PRECHARGE TERMINATION in READ Cycle
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2, the read data will remain valid until one clock after the precharge command. When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
T0 T1 T2 T3 T4 T5 T6 T7 Burst lengh= X T8
CLK
Command
Read
PRE tRP
ACT
CAS latency=2 DQ Q0 Q1 Q2 Q3 Hi-Z
command
Read
PRE tRP
ACT
CAS latency=3 DQ
Q0
Q1
Q2
Q3
Hi-Z
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10.2.2 Precharge Termination in WRITE Cycle
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
T0 CLK Command CAS latency = 2 DQM DQ D0 Write
T1
T2
T3
T4
T5
T6
T7
Burst lengh = X T8
PRE
ACT
D1
D2
D3
D4 tRP
Hi - Z
command CAS latency = 3
DQM
Write
PRE
ACT
DQ
D0
D1
D2
D3
D4
Hi - Z tRP
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VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Timing Diagram
Document :1G5-0177
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Mode Register Set
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
t RSC
CS
RAS
CAS
WE
BS0,1
A10
Address Key
ADD
DQM
t RP
DQ
Hi-Z
Precharge Command All Banks
Mode Register Set Command
Command
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AC Parameters for Write Timing (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5
T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CH t CL t CMS t CMH t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank B
CKE
t CKS
t CKH
CS
RAS
CAS
WE
*BS0
A10
t AS tAH
ADD
DQM
tRCD
DQ
t RRD tRC
tDAL
tDS t DH t DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank A Command Bank B Bank B Bank A
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
* BS1="L", Bank C,D = Idle
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AC Parameters for Write Timing (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t CL t CH t CK3 t CMS t CMH Begin Auto Precharge Begin Auto Precharge Bank A Bank B t CKH
CKE
t CKS
CS
RAS
CAS
WE
*BS0
A10
t AS t AH
ADD
DQM
tRCD
DQ
t RRD RC
t DAL
tDS t DH t DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write with Activate Write with Auto Precharge Command Auto Precharge Command Bank B Command Bank A Bank B
Activate Command Bank A
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
* BS1="L", Bank C,D = Idle
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AC Parameters for Read Timing (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=2, CAS Latency=2
T0 CLK
tCH tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK2 tCMS t CMH Begin Auto Precharge Bank B t CKH
CKE
tCKS
CS
RAS
CAS
WE
*BS0
A10
tAS tAH
ADD
tRRD tRAS tRC
DQM
t AC2 tLZ tAC2 tOH QAa0
t RCD
tHZ tOH QAa1 QBa0
tRP tHZ QBa1
DQ
Hi-Z
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
* BS1="L", Bank C,D = Idle
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AC Parameters for Read Timing (2 of 2)
T0 CLK
t CH tCL t CK3 t CMS t CMH
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=2, CAS Latency=3 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CKE
tCKS
Begin Auto Precharge Bank B
t CKH
CS
RAS
CAS
WE
*BS0
A10
t AH t AS
ADD
t RRD t RAS t RC t RP
DQM
t RCD
tAC3 tLZ
tAC3 tOH
tHZ tOH
QAa1 QBa0
t
HZ
DQ
Hi-Z
QAa0
QBa1
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
* BS1="L", Bank C,D = Idle
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Power on Sequence and Auto Refresh (CBR)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK CKE
High level is required t RSC Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
BS0, 1
A10
Address Key
ADD
DQM
High Level is Necessary t RP t RC
DQ
Hi-Z
Precharge Inputs Command All Banks must be stable for 200us
1st Auto Refresh Command
2nd Auto Refresh Command
Mode Register Set Command
Command
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VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycle
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
* BS1="L", Bank C,D = Idle
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VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycles
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
* BS1="L", Bank C,D = Idle
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VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
* BS1="L", Bank C,D = Idle
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VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Clock Suspension During Burst Write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 CLK
t CK3
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
* BS1="L", Bank C,D = Idle
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Power Down Mode and Clock Mask
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t t CKS
CKH
t CKS
CKE
VALID
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
ACTIVE STANDBY
Read Command Bank A Clock Mask Start Clock Mask End
Precharge Command Power Down Mode Entry
Precharge Standby
Power Down Mode Entry
Power Down Mode Exit
Power Down Mode Exit Command
* BS1="L", Bank C,D = Idle
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Auto Refresh (CBR)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0, 1
A10
RAa
ADD
RAa
CAa
DQM
t RP t RC t RC
Q0 Q1 Q2 Q3
DQ
Hi-Z
Precharge CBR Refresh Command Command All Banks
CBR Refresh Command
Activate Read Command Command
* BS1="L", Bank C,D = Idle
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Self Refresh (Entry and Exit)
CLK can be Stopped**
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 CLK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t SRX
t SRX
t CKS
CKE
t CKS
CS
RAS
CAS
WE
*BS0
A10
ADD
t RC t RC
DQM
DQ
Hi-Z
All Banks must be idle
Self refresh Entry
Self Refresh Exit
Self Refresh Entry Self Refresh Exit
Activate Command
* BS1="L", Bank C,D = Idle * Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
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VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Random Column Read (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
RAa RAd
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
QAd0 QAd1 QAd2 QAd3
Precharge Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Activate Read Command Command Command Bank A Bank A Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 42
VIS
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Random Column Read (Page With Same Bank) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
RAd
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 43
VIS
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Random Column Write (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Da1
Da2
Da3
Db0
Db1
Dc0
Dc1
Dc2
Dc3
Dd0
Dd1
Dd2
Dd3
Activate Command Bank B
Write Command Bank B
Write Write Command Command Bank B Bank B
Precharge Activate Write Command Command Command Bank B Bank B Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 44
VIS
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Random Column Write (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Da1
Da2
Da3
Db0
Db1
Dc0
Dc1
Dc2
Dc3
Dd0
Dd1
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 45
VIS
Random Row Read (Interleaving Banks) (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t t AC2 t RP
DQM
RCD
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
QBb0 QBb1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Active Command Command Bank B Bank B Read Command Bank A
Read Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 46
VIS
Random Row Read (Interleaving Banks) (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burs tLength=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t t RCD AC3 t RP
DQM
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Precharge Command Command Bank B Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 47
VIS
Random Row Write (Interleaving Banks) (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
DQM
t RCD
t DPL
t
RP
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Precharge Active Command Command Bank A Bank A Write Command Bank B
Write Command Bank A Precharge Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 48
VIS
Random Row Write (Interleaving Banks) (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
ADD
RBa
DQM
t DPL
t RP
t DPL
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Precharge Write Command Command Bank B Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 49
VIS
Read and Write Cycle (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
Hi-Z
DQ
QAa0 QAa1 QAa2 QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Write Command Bank A
The Write Data Write Command is Masked with a Bank A Zero Clock latency
Read Command Bank A
The Read Data is Masked with Two Clocks Latency
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 50
VIS
Read and Write Cycle (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
Hi-Z
QAa0 QAa1 QAa2 QAa3
DQ
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Read Command Bank A
Write The Write Data Read Command is Masked with a Command Bank A Bank A Zero Clock
Latency
The Read Data is Masked with Two Clock Latency
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 51
VIS
Interleaved Column Read Cycle (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
ADD
Ra
Cb
Ra
Ca
Cb
Cc
Cb
Cd
DQM
t
RCD
t AC2
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Command Bank A
Read Read Read Activate Read Read Read Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank B Precharge Command Bank A
Precharge Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 52
VIS
Interleaved Column Read Cycle (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
DQM
t RCD t RRD t AC3
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Read Command Bank A Activate Command Bank B
Read Read Read Read Precharge Precharge Command Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 53
VIS
Interleaved Column Write Cycle (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
Cb
DQM
t RCD
t RP
t DPL
t Hi-Z
RRD
DQ
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3
Activate Write Write Write Write Write Activate Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank A
Precharge Command Bank A Write Command Bank B
Precharge Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 54
VIS
Interleaved Column Write Cycle (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK3
CKE CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
Cd
DQM
t RCD
t DPL
t DPL
t Hi-Z
RRD
t RP
DQ
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Command Bank A
Write Command Bank A Activate Command Bank B
Write Write Write Write Write Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Precharge Command Bank A
Precharge Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 55
VIS
Auto Precharge after Read Burst (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK2
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
Rc
ADD
Ra
Ca
Ra
Ca
Cb
Rb
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate Read Activate Read with Command Command Command Auto Precharge Bank A Bank A Bank B Command Bank B
Read with Auto Precharge Command Bank A
Activate Command Read with Bank A Auto Precharge Command Read with Activate Bank B Auto Precharge Command Command Bank B Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 56
VIS
Auto Precharge after Read Burst (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t CK3
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2
Activate Command Bank A
Activate Command Bank B Read Command Bank A
Read with Auto Precharge Command Bank B
Read with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto precharge Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 57
VIS
Auto Precharge after Write Burst (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
Rc
ADD
Ra
Ca
Ra
Ca
Cb
Rb
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Activate Write Write with Activate Command Command Command Auto Precharge Command Bank A Bank B Bank A Bank B
Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A Auto Precharge Write with Bank A Auto Precharge Command Bank B
Start Auto Precharge Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 58
VIS
Auto Precharge after Write Burst (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK
t
CK3
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3
Activate Command Bank A
Activate Command Bank B Write Command Bank A
Write with Auto Precharge Command Bank B
Write with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto precharge Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 59
VIS
Full Page Read Cycle (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t RP
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 60
VIS
Full Page Read Cycle (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Full page burst operation does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 61
VIS
Full Page Write Cycle (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t BDL
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa+3 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 QBa+6
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B
Data is ignored Precharge Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Burst Stop Command
Activate Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 62
VIS
Full Page Write Cycle (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
tBDL Data is ignored.
DQ
Hi-Z
DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 63
VIS
Burst Read and Single Write Operation
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2 High
CKE CS
RAS
CAS
WE
*BS0
A10
RAa
ADD
RAa
CAa
CAb
CAc
CAd
CAe
DQM
Hi-Z
DQ
Activate Command Bank A
Read Command Bank A
Read Single Write Single Write Command Command Command Bank A Bank A Bank A
DQs are masked
Single Write Command Bank A
DQs are masked
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 64
VIS
Full Page Random Column Read
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BS
A10
Ra
Ra
Rb
ADD
Ra
Ra
Ca
Ca
Cb
Cb
Cc
Cc
Rb
t RP
DQM DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B
Read Command Bank B Read Command Bank A
Read Command Bank B
Read Command Bank A
Read Command Bank B
Precharge Command Bank B (Bank D) (Precharge Termination) Activate Command Bank B
Read Command Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 65
VIS
Full Page Random Column Write
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ra
Ca
Ca
Cb
Cb
Cc
Cc
Rb
t RP
DQM
DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B
Write Command Bank B Write Command Bank A
Write Command Bank B
Write Command Bank A
Write Command Bank B
Precharge Command Bank B (Bank D) (Precharge Termination) Write Data is masked Activate Command Bank B
Write Command Bank A
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 66
VIS
Precharge Termination of a Burst (1 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK2
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
CAc
t
DPL
t
RP
t
RP
t
RP
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Write Burst. Write data is masked.
Precharge Termination of a Read Burst.
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 67
VIS
Precharge Termination of a Burst (2 of 2)
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 CLK
t CK3
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BS0
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
t DPL
t
RP
t
RAS
t
RP
DQM
t
RCD
DQ
Hi-Z
DAa0 DAa1 QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Activate Command Bank A
Activate Command Bank A
Write Data is masked
Precharge Termination of a Write Burst.
Precharge Termination of a Read Burst.
* BS1="L", Bank C,D = Idle
Document :1G5-0177
Rev.2
Page 68
VIS
Ordering information Part Number VG366440(80/16)41DT(L)-6 VG366440(80/16)41DT(L)-7 VG366440(80/16)41DT(L)-7L VG366440(80/16)41DT(L)-8H
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Cycle time 6 ns (166MHz 3/3/3) 7 ns (143MHz 3/3/3) 7.5 ns (133MHz 3/3/3) 10 ns (100MHz 2/2/2)
Package
400mil, 54-Pin Plastic TSOP
VG36648041DT(L)-7L
* VG : VIS Memory Product * 36 : Technology/Design Rule * 64 : 64Mb * 80 : Device Configuration, 40:x4, 80: x8, 16: x16 *4 *1 *D *T *L : Device Infernal Banks : Interface Type, 1: LVTTL
: Mask/Design Version : Package Type, T: TSOP
: None: normal version; L:low power version
* 7L : Cycle time; -6 grade is available only on 4M X16 option
Packaging Information
* 400mil, 54-Pin Plastic TSOP
DIM A A1 A2 b b1 c c1 D ZD e E E1 L R R1
MILLIMETERS MIN. --0.05 0.95 0.30 0.30 0.12 0.12 22.09 NOM. ----1.00 --------22.22 0.71 REF. 0.80 BASIC 11.56 10.03 0.40 0.12 0.12 11.76 10.16 0.50 ----11.96 10.29 0.60 0.25 --0.455 0.395 0.016 0.005 0.005 MAX. 1.20 0.15 1.05 0.45 0.40 0.21 0.16 22.35 MIN. --0.002 0.037 0.012 0.012 0.005 0.005 0.870
INCHES NOM. ----0.039 --------0.875 0.028 REF. 0.0315 BASIC 0.463 0.400 0.020 ----0.471 0.405 0.024 0.010 --MAX. 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.880 b b1 E1 A1 L
RAD R1
54
28
A2
RAD R
B B
c
0X~8X
DETAIL A
SECTION B-B
c
1
D
27
c1
BASE METAL WITH PLATING
NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. b
ZD A
DETAIL A
e SEATING PLANE 0.100(0.004")
E
Document :1G5-0177
Rev.2
Page 69

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